Field of the Invention
Embodiments of the present invention relate to shadow ring modifications that enhance or otherwise affect the deposition of process gases on the edge and bevel of a wafer.
Description of the Related Art
Thermal and plasma enhanced chemical vapor deposition (CVD) are some of a number of processes used to deposit thin films of material on semiconductor wafers. To process wafers using thermal CVD, a vacuum chamber is provided with a substrate support configured to receive a wafer. In a typical CVD chamber, the wafer is placed into and removed from the chamber by a robot blade and is supported by a wafer support during processing. A precursor gas is delivered into the vacuum chamber through a gas manifold plate situated above the wafer, and the wafer is heated to process temperatures, generally in the range of about 250° C. to 650° C. The precursor gas reacts on the heated wafer surface to deposit a thin layer thereon and to form volatile byproduct gases, which are pumped away through the chamber exhaust system. In thermal CVD processes, a heater, such as an electrical resistance type heater may be used to heat the wafer. In plasma enhanced CVD (PECVD), one or more RF electrodes are provided to energize a gas to form a plasma. The heat to activate the precursors and form the thin film layer is provided by the plasma.
A primary goal of wafer processing is to obtain the largest useful surface area, and as a result the greatest number of chips, possible from each wafer. This is highlighted by the recent demands from semiconductor chip manufacturers to minimize edge exclusion on the wafers processed, so that as little of the wafer surface as possible, including the edge of the wafer, is wasted. Some important factors to consider include processing variables that affect the uniformity and thickness of the layer deposited on the wafer, and contaminants that may attach to the wafer and render all or a portion of the devices formed on the wafer defective or useless. Both of these factors should be controlled to maximize the useful surface area for each wafer processed.
One source of particle contamination in the chamber is material deposited at the edge or on the backside of the wafer that flakes off or peels off during a subsequent process. Wafer edges are typically beveled, making deposition difficult to control over these surfaces. Thus, deposition at wafer edges is typically non-uniform and, where metal is deposited, tends to adhere differently to a dielectric than to silicon. If a wafer's dielectric layer does not extend to the bevel, metal may be deposited on a silicon bevel and eventually chip or flake, generating unwanted particles in the chamber. Additionally, chemical mechanical polishing is often used to smooth the surface of a wafer coated with tungsten or other metals. The act of polishing may cause any deposits on the edge and backside surfaces to flake and generate unwanted particles.
A number of approaches have been employed to control the deposition on the edge of the wafer during processing. One approach employs a shadow ring which essentially masks or shields a portion of the perimeter of the wafer from the process gases. One disadvantage with the shadow ring approach is that, by masking a portion of the wafer's perimeter, the shadow ring reduces the overall useful surface area of the wafer. This problem is made worse if the shadow ring is not accurately aligned with the wafer, and alignment can be difficult to achieve. Further, the shadow ring itself affects the deposition uniformity in the region of the wafer's edge by drawing heat (from both resistive and plasma type heat sources) away from the edge of the wafer.
Accordingly a need exists for an improved shadow ring which can increase edge deposition uniformity and reduce the chance of particle contamination.